Embedding a KM type reducer for high speed fuzzy controller into an FPGA

Roberto Sepúlveda, Oscar Montiel-Ross, Oscar Castillo, Patricia Melin

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

2 Scopus citations

Abstract

There are many research works that have shown the advantages of type-2 fuzzy inference systems (T2-FIS) handling uncertainty with respect to type-1 fuzzy inference systems (T1-FIS); however, the use of a T2-FIS is still being controversial for several reasons, one of the most important is related to the resulting shocking increase in computational complexity that type reducers cause even for small systems, for example the Karnik-Mendel (KM) iterative method. The main goal of this paper is to show that the KM type reducer can be an efficient method if it is adequately implemented using the appropriate combination of hardware and software. In this work a novel architecture to implement the KM type reducer is shown, and in order to evaluate the architecture a comparative study was conducted. The study consisted in using a type-2 FIS programmed in Matlab to obtain some benchmarks, this to contrast the obtained results by testing the FIS programmed in VHDL for FPGA implementation. Preliminary studies have shown that the resulting speed up is in the order of 103, since a typical whole T2-inference (fuzzification, inference, KM-type reducer, and defuzzification) last 5 clock cycles; i.e., 0.1×10 -6 seconds for a Spartan 3 FPGA based system. Comparisons of the resulting control surfaces between T2-FIS programmed in Matlab and the FPGA implementation are also presented.

Original languageEnglish
Title of host publicationAdvances in Intelligent and Soft Computing
Pages217-228
Number of pages12
DOIs
StatePublished - 1 Dec 2010

Publication series

NameAdvances in Intelligent and Soft Computing
Volume75
ISSN (Print)1867-5662
ISSN (Electronic)1860-0794

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