TY - JOUR
T1 - Digital noise generator design using inverted 1D tent chaotic map
AU - Palacios-Luengas, Leonardo
AU - Duchen-Sánchez, Gonzalo Isaac
AU - Aragón-Vera, José Luis
AU - Vázquez-Medina, Rubén
PY - 2012
Y1 - 2012
N2 - This paper shows a digital noise generator designed in FPGA, based on a variant of the one-dimensional (1D) chaotic tent map (T-1D). The T-1D map is a piecewise linear 1D chaotic map that defines the statistical behavior of the generated sequences using its control parameter. In this way, the proposed noise generator is a highly competitive alternative in cryptographic systems when the statistical behavior of the sequences is closer to the uniform statistical distribution. The proposed system uses the inverted tent chaotic map (IT-1D), which has the same statistical behavior as the T-1D map. The fundamental algorithm used in this system was developed based on a 64-bit double precision format according to the numerical representation of floating point numbers defined in the IEEE-754 standard. The proposed system is analized using mechanical statistic tools and some statistical tests defined in the NIST 800-22SP (USA) standard. The main contribution of this work is the possibility of generating binary sequence of pseudorandom appearance by a procedure implemented in an FPGA device that translates real numbers to natural numbers preserving the statistical properties of sequences of real numbers that can be generated with the tent chaotic map in its original definition domain.
AB - This paper shows a digital noise generator designed in FPGA, based on a variant of the one-dimensional (1D) chaotic tent map (T-1D). The T-1D map is a piecewise linear 1D chaotic map that defines the statistical behavior of the generated sequences using its control parameter. In this way, the proposed noise generator is a highly competitive alternative in cryptographic systems when the statistical behavior of the sequences is closer to the uniform statistical distribution. The proposed system uses the inverted tent chaotic map (IT-1D), which has the same statistical behavior as the T-1D map. The fundamental algorithm used in this system was developed based on a 64-bit double precision format according to the numerical representation of floating point numbers defined in the IEEE-754 standard. The proposed system is analized using mechanical statistic tools and some statistical tests defined in the NIST 800-22SP (USA) standard. The main contribution of this work is the possibility of generating binary sequence of pseudorandom appearance by a procedure implemented in an FPGA device that translates real numbers to natural numbers preserving the statistical properties of sequences of real numbers that can be generated with the tent chaotic map in its original definition domain.
UR - http://www.scopus.com/inward/record.url?scp=84867961357&partnerID=8YFLogxK
U2 - 10.1155/2012/849120
DO - 10.1155/2012/849120
M3 - Artículo
SN - 1065-514X
VL - 2012
JO - VLSI Design
JF - VLSI Design
M1 - 849120
ER -