An efficient hardware implementation of a novel unary Spiking Neural Network multiplier with variable dendritic delays

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Abstract

We propose a novel unary spiking circuit for a serial multiplier with variable dendritic delays. Serial multipliers commonly use the soma model for the arithmetic operation. The structure of the serial multiplier and the efficient implementation of the dendritic delays on customized neuromorphic hardware are the major contributions of this work. The design of the multiplier was inspired by the biological processes of dendrites, which use feedback connections and dendritic growth to synchronize the neural processing performed by the soma. The multiplier eliminates complex rules by adopting the soma model with dendritic connectivity configurations, increasing the processing speed compared with previously reported solutions based on Spiking Neural Networks.

Original languageEnglish
Pages (from-to)130-134
Number of pages5
JournalNeurocomputing
Volume189
DOIs
StatePublished - 12 May 2016

Keywords

  • Dendritic delays
  • FPGA
  • Neuromorphic
  • Unary multiplier

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