TY - JOUR
T1 - A partitioned instruction queue to reduce instruction wakeup energy
AU - Ramírez, Marco A.
AU - Cristal, Adrián
AU - Valero, Mateo
AU - Veidenbaum, Alexander V.
AU - Villa, Luis
PY - 2004
Y1 - 2004
N2 - Instruction wakeup logic consumes a large amount of energy in out-of-order processors. Existing solutions to the problem require prediction or additional hardware complexity to reduce the energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a new mechanism for instruction wakeup, which uses a partitioned instruction queue (IQ). The energy consumption of an IQ partition (block) is proportional to the number of entries in it. All the blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed instruction for SPEC2000 benchmarks. The energy consumption and timing of the partitioned IQ design are evaluated using CACTI 3 models for a 0.07 pm process. The average energy savings observed were 85% and 92%, respectively, for 64-entry integer and floating-point partitioned IQs.
AB - Instruction wakeup logic consumes a large amount of energy in out-of-order processors. Existing solutions to the problem require prediction or additional hardware complexity to reduce the energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a new mechanism for instruction wakeup, which uses a partitioned instruction queue (IQ). The energy consumption of an IQ partition (block) is proportional to the number of entries in it. All the blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed instruction for SPEC2000 benchmarks. The energy consumption and timing of the partitioned IQ design are evaluated using CACTI 3 models for a 0.07 pm process. The average energy savings observed were 85% and 92%, respectively, for 64-entry integer and floating-point partitioned IQs.
KW - CAM
KW - instruction wakeup
KW - instruction window
KW - low power
KW - out-of-order execution
KW - superscalar processors
UR - http://www.scopus.com/inward/record.url?scp=84951716056&partnerID=8YFLogxK
U2 - 10.1504/IJHPCN.2004.008344
DO - 10.1504/IJHPCN.2004.008344
M3 - Artículo
SN - 1740-0562
VL - 1
SP - 153
EP - 161
JO - International Journal of High Performance Computing and Networking
JF - International Journal of High Performance Computing and Networking
IS - 4
ER -