In this paper, an efficient architecture for multiplicative inversion in GF(2 m) using addition chains is presented. The approach followed was based on the Itoh-Tsujii algorithm targeting a fast implementation on reconfigurable hardware devices. We give the design details of the proposed architecture whose main building blocks are a field multi-squarer block, a field polynomial multiplier and a BRAM two-ports memory. Our design is able to compute multiplicative inversion in GF(2 193) in about 1.33μS using only 27 clock cycles. © 2005 IEEE.
|Original language||American English|
|Number of pages||516|
|State||Published - 22 Sep 2005|
|Event||International Conference on Information Technology: Coding and Computing, ITCC - |
Duration: 22 Sep 2005 → …
|Conference||International Conference on Information Technology: Coding and Computing, ITCC|
|Period||22/09/05 → …|
Rodríguez-Henríquez, F., Saqib, N. A., & Cruz-Cortés, N. (2005). A fast implementation of multiplicative inversion over GF(2 m). 574-579. Paper presented at International Conference on Information Technology: Coding and Computing, ITCC, .