A digital real time image demosaicking implementation for high definition video cameras

Jair Garcia-Lamont, Miguel Aleman-Arce, Julio Waissman-Vilanova

Research output: Contribution to conferencePaperpeer-review

6 Scopus citations

Abstract

This paper describes a digital real time image demosacking implementation for high definition video cameras. It comprises one buffer for three pixel rows and one interpolator based on bilinear interpolation. It has been implemented with HDL-Verilog and mapped onto Virtex-4 XC4VLX25 from Xilinx; for a clock frequency of 150MHZ, its throughput is 72 frames per second. This implementation may be used as an intellectual property for FPGA's or SoC.

Original languageEnglish
Pages565-569
Number of pages5
DOIs
StatePublished - 2008
EventProceedings - 5th Meeting of the Electronics, Robotics and Automotive Mechanics Conference 2008, CERMA 2008 - Cuernavaca, Morelos, Mexico
Duration: 30 Sep 20083 Oct 2008

Conference

ConferenceProceedings - 5th Meeting of the Electronics, Robotics and Automotive Mechanics Conference 2008, CERMA 2008
Country/TerritoryMexico
CityCuernavaca, Morelos
Period30/09/083/10/08

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