Abstract
This paper describes a digital real time image demosacking implementation for high definition video cameras. It comprises one buffer for three pixel rows and one interpolator based on bilinear interpolation. It has been implemented with HDL-Verilog and mapped onto Virtex-4 XC4VLX25 from Xilinx; for a clock frequency of 150MHZ, its throughput is 72 frames per second. This implementation may be used as an intellectual property for FPGA's or SoC.
Original language | English |
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Pages | 565-569 |
Number of pages | 5 |
DOIs | |
State | Published - 2008 |
Event | Proceedings - 5th Meeting of the Electronics, Robotics and Automotive Mechanics Conference 2008, CERMA 2008 - Cuernavaca, Morelos, Mexico Duration: 30 Sep 2008 → 3 Oct 2008 |
Conference
Conference | Proceedings - 5th Meeting of the Electronics, Robotics and Automotive Mechanics Conference 2008, CERMA 2008 |
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Country/Territory | Mexico |
City | Cuernavaca, Morelos |
Period | 30/09/08 → 3/10/08 |